Gate Driver On Array (GOA) technology is a kind of technology that the thin film transistor liquid crystal display array (Array) process is utilized to manufacture the Gate row scan drive signal circuit on the array substrate to realize the drive manner to scan the gates row by row.
As designing the GOA circuit according to prior art, the output row by row of the gate is realized by multiple cascaded levels manner. Please refer to FIG. 1, which is a diagram of a GOA circuit according to prior art. The GOA unit correspondingly outputs the horizontal scan signal of nth row in the upper part in FIG. 1, and the GOA unit correspondingly outputs the horizontal scan signal of n+1th row in the lower part in FIG. 1. The nth level GOA unit is illustrated to describe the structure of the GOA circuit according to prior art. The GOA circuit of prior art comprises a plurality of GOA circuit units which are cascade coupled, wherein the nth level GOA circuit unit outputting a nth row horizontal scan signal comprises: a first thin film transistor T1, of which a gate is coupled to a signal output point Gn−2 of the n−2th level GOA circuit unit, and a source and a drain are respectively coupled to a node Hn and inputted with a forward scan control signal U2D; a second thin film transistor T2, of which a gate is coupled to the node Qn, and a source and a drain are respectively coupled to a signal output point Gn of the nth level GOA circuit unit and inputted with a clock signal CKV1; a third thin film transistor T3, of which a gate is coupled to a signal output point Gn+2 of the n+2th level GOA circuit unit, and a source and a drain are respectively coupled to the node Hn and inputted with the forward scan control signal D2U; a fourth thin film transistor T4, of which a gate is coupled to a node Pn, and a source and a drain are respectively coupled to the signal output point Gn and the constant low voltage level VGL; a fifth thin film transistor T5, of which a gate is coupled to a constant high voltage level VGH, and a source and a drain are respectively coupled to the node Hn and a node Qn; a sixth thin film transistor T6, of which a gate is coupled to the node Pn, and a source and a drain are respectively coupled to the node Hn and the constant low voltage level VGL; a seventh thin film transistor T7, of which a gate is coupled to the node Hn, and a source and a drain are respectively coupled to the node Pn and a constant low voltage level VGL; an eighth thin film transistor T8, of which a gate is inputted with a clock signal CKV3, and a source and a drain are respectively coupled to the node Pn and the constant high voltage level VGH; a first capacitor C1, of which two ends are respectively coupled to the node Qn and the signal output point Gn; a second capacitor C2, of which two ends are respectively coupled to the node Pn and the constant low voltage level VGL. The point Q (i.e. Qn) is the point employed to control the output of the gate drive signal; the node point P (i.e. Pn) is the point employed to maintain the stability of the low voltage levels of the point Qn and the point Gn. The dotted lines portion in FIG. 1 is a forward-backward scan unit of the GOA circuit. The circuit structure of the n+1th level GOA circuit unit is similar with that of the nth level. The description is omitted here.
Please refer to FIG. 2, which is a forward scan sequence diagram of the GOA circuit in FIG. 1. With combination of FIG. 1, the specific work process (forward scan) of the circuit is introduced below:
the output of the level Gn is illustrated; as forward scan, U2D is high voltage level, and D2U is low voltage level;
stage 1, pre-charge stage, Gn−2 and U2D are high voltage levels at the same time, and T1 is on, and the point Hn is pre-charged. As the point Hn is the high voltage level, T5 is in an on state, and the point Qn is pre-charged. As the point Hn is the high voltage level, T7 is in an on state, and the point Pn is pulled down;
stage 2, Gn outputs high voltage level: in stage 1, the point Qn is pre-charged, and C1 has a certain maintaining function to the electrical charges, and T2 is in an on state, and high voltage level of CKV1 is outputted to the end Gn;
stage 3, Gn outputs low voltage level: C1 has the maintaining function to the high voltage level to the point Qn, and the low voltage level of CKV1 pulls down the point Gn;
stage 4, the point Qn is pulled down to VGL: as Gn+2 is high voltage level, D2U is low voltage level, and T3 is in an on state, and thus, the point Qn is pulled down to be VGL;
stage 5, the point Qn and the point of Gn maintain low voltage level: after the point Qn becomes low voltage level, T7 is in an off state, and as CKV3 jumps to high voltage level, T8 is on, and the point Pn is charge, and then both T4 and T6 are in an on state, which can ensure the low voltage level stabilities of the point Qn and the point Gn, and meanwhile, C2 has a certain maintaining function to high voltage level of the point Pn.
Certainly, the output principle of the Gn+1 level is similar with the output of the Gn level but only the control sequence circulates according to a certain rule.
Please refer to FIG. 3, which is a backward scan sequence diagram of the GOA circuit in FIG. 1. With combination of FIG. 1, the specific work process (backward scan) of the circuit is introduced below:
the output of the level Gn is illustrated; as forward scan, U2D is high voltage level, and D2U is low voltage level;
stage 1, pre-charge stage, Gn+2 and D2U are high voltage levels at the same time, and T3 is on, and the point Hn is pre-charged. As the point Hn is the high voltage level, T5 is in an on state, and the point Qn is pre-charged. As the point Hn is the high voltage level, T7 is in an on state, and the point Pn is pulled down;
stage 2, Gn outputs high voltage level: in stage 1, the point Qn is pre-charged, and C1 has a certain maintaining function to the electrical charges, and T2 is in an on state, and high voltage level of CKV1 is outputted to the end Gn;
stage 3, Gn outputs low voltage level: C1 has the maintaining function to the high voltage level to the point Qn, and the low voltage level of CKV1 pulls down the point Gn;
stage 4, the point Qn is pulled down to VGL: as Gn−2 is high voltage level, U2D is low voltage level, and T1 is in an on state, and thus, the point Qn is pulled down to be VGL;
stage 5, the point Qn and the point of Gn maintain low voltage level: after the point Qn becomes low voltage level, T7 is in an off state, and as CKV3 jumps to high voltage level, T8 is on, and the point Pn is charge, and then both T4 and T6 are in an on state, which can ensure the low voltage level stabilities of the point Qn and the point Gn, and meanwhile, C2 has a certain maintaining function to high voltage level of the point Pn.
Certainly, the output principle of the Gn+1 level is similar with the output of the Gn level but only the control sequence circulates according to a certain rule. In one aspect, according to the development of LCD at present, the narrow frame becomes more and more popular, and particularly the decrease of the left, right borders. As designing the GOA circuit according to prior art, the output row by row of the gate is realized by multiple cascaded levels manner. The GOA circuit is shown in FIG. 1, and the corresponding outputs of the Gn+1, Gn levels, the detail sequence are shown in FIG. 2 and FIG. 3. The full high resolution display (FHD) Interlace drive manner is illustrated. the single side has the gate outputs of 960 levels, which correspond to the layout of 480 levels shown in FIG. 1. As the left, right borders constantly decreases, the GOA circuit design of prior art might not satisfy the design requirement.
In another aspect, for satisfying the requirement of image high quality sometimes, most of the Data drives utilize the Dot Inversion manner. Namely, the data signal has to jump high and low constantly, the power consumption for the Dot Inversion is relatively higher, and the calculation formula of the power consumption is below:P=½*C*f*V2 
C is the capacitor, and f is the frequency, and V is the voltage.